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Bizen the results (ten years back to the future) ZTL vs CMOS

Bizen ZTL vs CMOS

This article covers the initial ZTL logic technology based on Bizen and the planar Zpolar transistor, first published 2022.

CMOS has been dynamite for the industry creating huge sucess and growth. We too grew up with CMOS, we are fans. This article is not setting out to criticize that sucess but rather provide an alternative to help the industry. The reference to CMOS is to aid education.

ZTL has now been superseded by VZTL. The vertical version. A brief insight into VZTL can be found on the home page. We have left this article for detailed reference. 

SFN (Search for the Next) set out to transform the entire electronics industry by going back to where semiconductors began and taking a fresh look at the physics which led to the original bipolar path. This analysis opened up a new direction based on tunnel mechanics as the best way forward. The result is the compound combination Bizen® wafer process, Zpolar® Transistor and Zpolar Tunnel Logc. We have made bold claims for Bizen. We have said that with Bizen, manufacturing time is reduced by 75%, frequency per Watt increased ten times and die size cut so much over CMOS that outmoded FABS are brought back into competition with the State of the Art, or moved beyond horizons not yet imagined. This report is the product of years of testing, proving and exceeding the claims we have made.

With Bizen, SFN has effectively given industry a time machine. Figure 1 is helpful here. The black text shows the situation for all processes across time, whereas the purple text shows the benefits of Bizen Zpolar Tunnel Logic (ZTL) expressed as a CMOS geometry equivalence. The green text shows the ZTL possible speed benefit. Figure 1 shows that in 1990 state-of-the-art transistor manufacturing was one micron (1µm). 10 years later, in 2000, it's 180nm and in 2010, around 25/28nm. Today we're looking at 5nm and below. Or to put it another way, approximately seven process nodes per decade. IC producers can use Bizen transistors, either to jump back - say ten years to take a common roadmap point - and produce devices on cheap, available process lines at fabs that most would regard as obsolete, or we believe bypass any roadmap performance strategies from even Intel or TSMC achieving hitherto unseen performance gains without waiting 10 years for the processing to catch up. For example 5G requires a 25nm FAB which exists only overseas. Applying ZTL to the Newport FAB would allow the UK to manufacture 10-25nm CMOS equivalent 5G chips on 180nm domestically which results in a cost, speed and level of performance that is world beating. Bizen has successfully been adopted into the existing foundry infrastructure and EDA tools. (Electronic design automation e.g. Cadence). The Bizen ZTL value add is the PROs without the CONs without waiting a decade.


Figure 1

area chart vs geometry


That's why we use the 'time-machine' analogy. Engineers have been very resourceful and ingenious in finding new ways to develop device structures such as FinFETs which squeeze a little more performance for CMOS. But at huge cost. That's why so very few companies can afford to have state-of-the-art, single-figure nanometre fabs.


Figure 2 


3D Cone Diagram PORPDKLIB 500

With its ZTL, Zpolar Tunnel Logic, SFN is addressing the commercial manufacturing and lead time issues that CMOS and subsequent technologies have not. But obviously, for a chip made using, say, a one micron Bizen process, the ZTL would need the performance of a device made in 28nm CMOS, i.e. approximately 30 times smaller and ten times faster than CMOS on 180nm. The result could yield 150 fold reduction in cost. Figure 2 is a graphical representation of the Bizen 'time machine': the technology can operate horizontally ‘x’ across all markets, vertically ‘y’  through the segments, re-enable industry ‘z’, impacting everything through time since the creation of MOS ‘t’.

To accomplish the design of the new transistor and tunnel mechanics, all segments of the industry, from the very physics foundation up, required a polar opposite ethos: moving from the designers dream to a manufactures dream of risk, cost, time, and resources.

The Bizen product categories include:

  • The foundation POR is the Bizen ‘Process of Reference’ for the wafer process with tunnel mechanics, every step owned, patented and unique to SFN.
  • The PDK are the Bizen devices ‘Process Development Kit’ including the Zpolar Transistor and tunnels, patented and unique to SFN.
  • The LIB are the Bizen cell ‘libraries’ including the Zpolar Tunnel Logic (ZTL) family, patented and unique to SFN.
  • $$$$$ from end products.

So let's look at size and speed. Figure 3 depicts the area required for three logic gates (NOR2, NOR2 and NAND2) in a one micron CMOS process, showing the size and complexity of the problem. The MOS transistor itself might be small, but when used in a CMOS gate, that's where the problems arise, because in CMOS you have a push and pull transistor so you need to have two transistors per input and tracks between them. The three gates in Figure 3 are made of four transistors per gate, 12 MOS transistors in total which in this arrangement, made on a one 180nm micron process, takes an overall space of 84.4 µm2.

The comparison with Bizen Zpolar transistors - which do not need this push-pull structure to form gates - is stark. By having no requirement for complementary transistors, Bizen has a size advantage because it uses fewer transistors and has a resulting reduction in interconnect count. Initial results on a D-type flip flop showed a size reduction of 3x using the basic Bizen transistor compared to the equivalent CMOS gate. When tunnelling was added, the improvement led to a 9.3x reduction in size through a further decrease in the number of transistors needed and the use of inherent tunnelling. The now fully characterised Zpolar Transistor with tunnel mechanics, and reduced current density, form the Zpolar Tunnel Logic (ZTL) family gates that are 30x smaller (Figure 4) at 2.86 µm2.  


Figure 3

Cell size comparison

Figure 4

The speed enhancement is due to the phenomenal transconductance of the Zpolar transistor. When combined with tunnel mechanics, which applies constant current to transconductance, this gives you huge voltage gains - up to 1000. To put that into context, we found the voltage gain for a space saving lateral BJT to be sub ten and as CMOS uses two MOS transistors, the input is two narrowly controlled voltages centred by an undefined prohibited range which will either cause shoot through or an undefined state making the gain undefined and with a limit on maximum speed.

The output of the Zpolar transistor is very, very fast and nearly square. This is because of the massive transconductance gain even when well or junction capacitance is taken into account. And that is the trick - turn on and turn off are nearly instantaneous. With CMOS, to turn the transistor on, the saw-tooth input wave form would have to go nearly all the way to the top. And then to turn it off, you would go all the way to the bottom. You have to suffer this edge, slowed down by capacitance, and you've got to swing across two transistors.  You’ve got no choice. With ZTL, because the transconductance gain is massive and we don't need two transistors per gate you can have a very small signal, so any capacitance which slows you down is far, far less. This is where the CMOS guys - the push/pull guys - got it wrong, they were pushing and pulling across large voltage potentials: graphene, phosphorene and electron flip all have the same problem. ZTL, therefore allows ICs to run at much faster speeds, effectively giving the performance of a device made using much finer geometries.

Figure 6 shows this performance using the example of an inverter gate in ZTL. Whereas normal CMOS exhibits about 1.2 volts output voltage swing at a minimum, ZTL needs only 170mV, producing a gate that achieves 3GHz - on a one micron process – as an example of linear power increase, see Figure 10. Just imagine how fast it would go on 180nm? And it can be scaled from there too; latest technology nodes will result in devices operating at tens or possibly hundreds of gigahertz.

Those with experience in CMOS may realise that a similar effect can be done by shifting the threshold voltages of the MOS transistors, however this method has a major flaw that is shoot-through current. In Figure 7, the current being delivered to the load capacitance is much less than the total current, and 6.7uA of current is lost to shoot through. Shoot through current increases power consumption dramatically as speed increases and enforces a maximum frequency on CMOS.


Figure 6

Figure 6

ZTL gate: As the input voltage (blue) moves from 325mV (logic level 1) to 375mV (logic level 0) (50mV swing), the output voltage (green) completes a logic swing from logic level 0 to logic level 1. In-between the two voltages is undefined. The next inverter (red) shows the high transconductance of Zpolar, providing the combinational logic speedup.


Figure 7

Figure 7

CMOS Logic Gate: The useful current used to charge the gate capacitance (Green) and the total current driven through the top transistor (Red) and bottom transistor (Blue). The additional 6.7uA of total current above the useful current is lost to shoot-through, which ultimately limits the maximum frequency.

The following timing diagrams are for a 1um Bizen process.

In Figure 8, Readers will notice that the current spike up and down is the same for Zpolar as it is for CMOS (Figure 9). The unique features of the Zpolar, the way it works with tunnel mechanics, allows us to create what appears to be a push/pull but it isn't, it’s balanced.

Figure 8

Figure 8

Figure 9

Figure 9

In CMOS logic, you’re basically using the DC characteristics only, on and off, pushing and pulling high and low voltage - it’s DC physics. Tunnel mechanics has an AC characteristic as well, so it combines AC theory as well as DC theory, and capacitances that cancel each other out.

Delving deeper we see that the outputs are very square (Figure 10).  Rise and fall times of around 45 picoseconds, and a propagation delay - how long it takes to go from one inverting gate to the next - of just 12.5 picoseconds - remember this is using a one micron fabrication process. That's why the signal speed is up at 3GHz. We are intentionally showing wide and thin pulses to demonstrate that even though we are using AC/DC theory, we still are able to have infinitely long logic states followed by a pulse at very high speed, and back again, replicating logic behaviour where you sit in one state for ages, then suddenly switch low and back high again. What we are showing is not just some RF clock, we're showing a non-symmetrical mark space signal, i.e., a DC component, it’s longer higher than it is low. It still works. When people have looked at trying to use RF before for logic, it performed OK with continuously balanced 50/50-mark space ratio clocks, but not with more typical, non-clock logic signals. With ZTL, you can.


Figure 10

Figure 10


For ZTL, frequency is linear with power and inverse capacitance as described by the following equation.



Capacitance scales with geometry size.

For CMOS, frequency has an extra parameter of shoot through current and difficulty reducing capacitance with drive power, which results in a non-linear curve and a practical limit on maximum frequency.


 Figure 11

Figure 11

The above CMOS power vs speed graph is supported by the fact that one method to address the shoot-through is to increase the separation between low and high side threshold voltages. A way to do this is to increase the supply voltage but that again results in increased power dissipation and only extends the maximum frequency a small amount given the nonlinear curve for power vs frequency.

 This can be seen here even on the modern geometry nodes used by the i7 processor.

We have created new symbols (Figure 14) that represent the tunnels and the transistors. Combined with the fully characterised component models that have come straight off the wafer. We no longer use conventional electronics such as BJT, MOS, JFET, Resistors, Capacitors. We only use Zpolar transistors and tunnel mechanics to design our circuits, whether it's an op amp, a comparator or logic gate, using our symbols and models. The SFN held the first day of the last this year i.e., the first day of the last day for conventional electronics.


Figure 14

Figure 14


The Bizen process is an eight layer process that can be produced in a theoretical foundry time of 7.5 days. Bizen takes advantage of having lower peak currents, improved current density and no issues creating fields with crossing active area and metal tracks while also implementing inherent tunnel mechanics allowing improved use of the substrate, polysilicon and other routing layers.

The simplicity of the Bizen process, which has a low mask count of eight and low number of processing steps of ten required per mask, reduces time, resources, cost and risk during manufacture.

For comparison, the lowest mask count we envisage for 1um CMOS is around 13 layers, and implant count would be approximately double our four implants, so the total number of process steps for CMOS is around double Bizen's total process steps at the same geometry node.

This is compounded by the fact that in order to match the speed and density achieved by Bizen, a CMOS circuit needs to be manufactured on a finer process node, maybe 10 years newer, which means the number of masks and process steps, and hence cost and time to produce, are also greatly increased compared with Bizen. As process geometry shrinks, the required amount of mask layers and process steps increases disproportionately, for example a 250nm CMOS process may have as many as 24 mask layers and 400 total process steps.


Figure 15

Figure 15




Using the linear speed of ZTL to create 20 year time shift of CPU speed without CAPEX.

Chiplets are small chips performing part of the function of a single SoC chips. ZTL can take advantage of this approach, by offering faster performance on functional blocks where required, avoiding the need for Extreme UV-processed chips at 7nm or below.

Using a 180nm foundry such as UK’s Newport wafer foundry, ZTL will provide an equivalent CMOS geometry of 25nm.   If 4nm is currently used for CMOS, a larger ZTL die could be used achieving the same switching speed at the 180nm node. This combination allows Newport to produce cutting edge chips, at 150 times lower cost and a fraction of the lead time.

Furthermore, manufacturing on finer geometries requires either deep UV, which needs Neon gas for the pattern transfer tool light source,  or when even finer, extreme UV which needs the single-sourced (ASML) exposure tool. Ukraine produces about 70% of the world’s neon gas which is now in short supply as the country finds itself at war with its neighbour, Russia. This has curtailed production and exacerbated the already short supply of ICs in the semiconductor industry. 

SFN does not have this issue. Bizen can be manufactured using its 30:1 size reduction enabling advanced technologies like 5G to be produced without the need for neon gas and in British foundries.

SFN is ready to engage now with companies who wish to enjoy the game-changing benefits of Bizen and ZTL. The company owns the transistor IP, the wafer process and the device library with the application circuits.  Gold standard process results and DSIM where required exist at every step so everything is characterised and targeted to production standard.

So it doesn't matter what a company may have on its road map. The size and performance that is being predicted for 10 years' time they can have today. As Allan James, Semefab's CEO said: "Bizen has the potential to wind back Moore's Law 10 years." But it could also wind it forward.


ZTL vs CMOS – A Like-for-Like Comparison

To give a concrete example of what can be done in ZTL, we can make a Pentium II on a 1um process node with equivalent performance and power consumption to a 350nm CMOS process using only eight mask layers, in just eight days.

Below is a table which in the left two column compares CMOS against the right three columns in ZTL.

The orange square indicates the matching parameter while the green squares represent the improvements switching from CMOS to ZTL. We have chosen a Pentium II as the performance figures are public domain and well known. The Ten years is applicable to modern geometry foundries as well, allowing a leap forward in time with no foundry CAPEX.



The following graphs back up the table using spice models in Cadence Virtuoso derived from characterised devices analysed with JMP from physical wafers that were designed at physics level using Synopsys Sentaurus TCAD.

Synopsys Sentaurus TCAD has already modelled the Bizen devices on geometry’s from 1um to 180nm, showing that the technology is scalable.

  • Bizen can be adopted by existing foundry infrastructure and EDA tools.
  • Standard libraries and PDK are in development for Cadence Virtuoso.
  • Extensive repository of measured electronic characterisation data of Bizen devices, obtained using advanced test equipment, from multiple physical wafer batches produced over three years in a full production facility.
  • Detailed manufacturing process flow for the Bizen wafer process, with practical foundry feedback, physical analysis and tolerancing.
  • A Bizen device characterisation data book exists in JMP.
  • SPICE models have been created from physical wafer data, analysed in JMP.
  • Process flow and physics models exist in Synopsys Sentaurus TCAD.


1.      Version 1: Bizen 1um process matching speed to 1um equivalent Pentium II process – Graphs and Data



Fig. 1.1: Inverter chain timing diagram, green is the input of the 1st gate, red waveform is the output of the 10th gate. Clocking speed is 38MHz.




Fig. 1.2: Inverter input (Blue) and output (Green) waveforms showing rise and fall times.




Fig. 1.4: Charge and Discharge current of the Well Capacitance at 5MHz


2.      Version 2: Bizen 1um process matching power to 1um equivalent Pentium II process – Graphs and Data


Fig. 2.1: Inverter chain timing diagram, blue is the input of the 1st gate, red waveform is the output of the 10th gate. Clocking speed is 200MHz.




Fig. 2.2: Inverter input (Blue) and output (Red) waveforms showing rise and fall times.



Fig. 2.4: Charge and Discharge current of the Well Capacitance at 5MHz



Version 3: Bizen 1um process Maximum Speed – Graphs and Data



Fig. 3.1: Inverter chain timing diagram, green is the input of the 1st gate, red waveform is the output of the 10th gate. Clocking speed is 1GHz.




Fig. 3.2: Inverter chain timing diagram, green is the input of the 1st gate, blue waveform is the output of the 10th gate. Clocking speed is 3GHz.




Fig. 3.3: Inverter input (Blue) and output (Green) waveforms showing rise and fall times.


Pentium II References

General Pentium II info:


Other info:







Process Of Reference

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The process of reference ‘POR’ defines the physics of the Bizen wafer process.



Process Development Kit

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The process development kit, PDK, are the Bizen devices PDK including the Zpolar Transistor and tunnels.



Library Cells

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The Bizen cell libraries including the Zpolar Tunnel Logic (ZTL) family.